References & Further Reading

Academic papers, books, and open-source projects that informed OpenNANDLab’s design.

Core References

Kim et al. (2009). “A Survey of Flash Translation Layer.” Journal of Computer Science and Technology, 24(6), 1167–1183.
The canonical FTL survey. Covers page mapping, block mapping, hybrid FTL, and log-structured FTL.
Agrawal et al. (2008). “Design Tradeoffs for SSD Performance.” USENIX ATC.
Systematic analysis of how FTL policy choices affect throughput, latency, and WAF.
Park et al. (2006). “A High-Performance Controller for NAND Flash-based Solid State Disk (NSSD).” NVSMW.
Hardware controller architecture with integrated bad-block management and wear leveling.

Bux & Iliadis (2010). “Performance of Greedy Garbage Collection in Flash-based Solid-State Drives.” Performance Evaluation, 67(11), 1172–1186.
Analytical model for greedy GC WAF under various write patterns.
Chiang et al. (1999). “Using Data Clustering to Improve Cleaning Performance for Flash Memory.” Software: Practice and Experience, 29(3), 267–290.
Hot/cold data separation approach to reduce GC overhead.

Chang & Chang (2008). “A Self-Balancing Striping Scheme for NAND-Flash Storage Systems.” SAC.
Striping-based wear leveling for multi-chip devices.
Chang & Chang (2007). “Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design.” DAC.
Static wear leveling that forces cold data out of under-worn blocks.

Lin & Costello (2004). Error Control Coding: Fundamentals and Applications (2nd ed.). Prentice Hall.
Definitive textbook for BCH code theory, Galois field arithmetic, Berlekamp–Massey, Chien search, and Forney’s algorithm.
Gallager, R. G. (1963). “Low-Density Parity-Check Codes.” IRE Transactions on Information Theory, 9(1), 21–28.
Original LDPC paper.
Qiao Li et al. (2024). “Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories.” ACM Transactions on Architecture and Code Optimization.
Modern analysis of LDPC soft-decision decoding on 3D NAND; motivates the Gaussian threshold-voltage LLR model.
DOI: 10.1145/3663478

Luo et al. (2018). “Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation.” arXiv:1807.05140.
CMU SAFARI paper. Documents layer-to-layer variation, early retention loss, and read-disturb patterns specific to 3D NAND. Motivates the per-cell reliability model.
Cai et al. (2017). “Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery.” arXiv:1710.08898.
Comprehensive error taxonomy: P/E wear, retention, read disturb, program interference. Reference for the RBER model.
Grupp et al. (2009). “Characterizing Flash Memory: Anomalies, Observations, and Applications.” MICRO-42.
Empirical characterization of raw NAND error rates across devices and wear levels.

Hu et al. (2009). “Measuring and Analyzing Write Amplification Characteristics of Solid State Disks.” MASCOTS.
Measurement study showing WAF under different workloads and OP levels.

NVM Express Base Specification (2023). Version 2.0c. nvmexpress.org.
Definitive reference for NVMe submission/completion queue model.
JEDEC JESD79F — ONFI NAND Flash Interface Specification.
Command timing model (tR, tPROG, tBERS) used in the timing module.

Project	URL	Language	Notes
MQSim	https://github.com/CMU-SAFARI/MQSim	C++	CMU SAFARI — NVMe/SATA SSD simulator; most complete open-source reference
Dhara	https://github.com/dlbeer/dhara	C	Embedded NAND FTL for low-memory systems; O(log n) worst-case
NAND Dump Tools	https://github.com/SySS-Research/nand-dump-tools	Python	BCH ECC for raw NAND dump forensics
nandtool	https://github.com/NetherlandsForensicInstitute/nandtool	Python	ECC correction for arbitrary NAND configurations
DiskSim	https://github.com/westerndigitalcorporation/DiskSim	C	Storage system simulator (HDD-era but useful for methodology)

Book	Authors	Relevance
Error Control Coding	Lin & Costello	BCH, LDPC theory
The Art of Computer Systems Performance Analysis	Jain	Benchmarking methodology, percentile statistics
Operating Systems: Three Easy Pieces	Arpaci-Dusseau	Flash chapter; storage stack context
Computer Organization and Design	Patterson & Hennessy	Memory hierarchy; cache replacement policies

Dataset	Source	Use case
Microsoft SNIA traces	https://iotta.snia.org	Real-world enterprise I/O traces for trace replay
FIO synthetic traces	https://github.com/axboe/fio	Configurable synthetic I/O with JSON output
FAST conference datasets	https://www.usenix.org/conference/fast25	Research-grade storage traces

If you use a paper to motivate a new feature, add it here in the same format.